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    WSC
    1997
    151views Modeling And Simulation» more  WSC 1997»
    Efficient Instruction Cache Simulation and Execution Profiling with a Threaded-Code Interpreter
    14 years 5 months ago
    Efficient Instruction Cache Simulation and Execution Profiling with a Threaded-Code Interpreter
    Download  www.informs-sim.org
    We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
    Peter S. Magnusson
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