Sciweavers

    DAC
    2007
    ACM
    131views Computer Architecture» more  DAC 2007»
    Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
    14 years 12 months ago
    Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
    Download  cobweb.ecn.purdue.edu
    This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
    Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
    claim paper
    Read More »
    Explore & Download
    Proceedings Preprints Top 5 Ranked Papers Publications Books Software Tutorials Presentations Lectures Notes Datasets
    Productivity Tools
    International On-screen Keyboard Graphical Social Symbols OCR Text Recognition CSS3 Style Generator Web Page to PDF Web Page to Image PDF Split PDF Merge Latex Equation Editor Sci2ools
    Document Tools
    PDF to Text PDF to Postscript PDF to Thumbnails Excel to PDF Word to PDF Postscript to PDF PowerPoint to PDF Latex to Word Repair Corrupted PDF
    Image Tools
    JPG to PS JPG to PDF Extract Images from PDF Image Converter
    Sciweavers
    About Community Cookies Privacy Policy Terms of Use

    Copyright © Sciweavers LLC, 2009-2024, USA.