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SAC
2010
ACM
13 years 9 months ago
A machine-checked soundness proof for an efficient verification condition generator
Verification conditions (VCs) are logical formulae whose validity implies the correctness of a program with respect to a specification. The technique of checking software properti...
Frédéric Vogels, Bart Jacobs 0002, F...
HVC
2007
Springer
106views Hardware» more  HVC 2007»
14 years 3 months ago
Exploiting Shared Structure in Software Verification Conditions
Abstract. Despite many advances, today's software model checkers and extended static checkers still do not scale well to large code bases, when verifying properties that depen...
Domagoj Babic, Alan J. Hu
CAV
2007
Springer
112views Hardware» more  CAV 2007»
14 years 3 months ago
Structural Abstraction of Software Verification Conditions
al Abstraction of Software Verification Conditions Domagoj Babi
Domagoj Babic, Alan J. Hu