Sciweavers

WSC
1998
14 years 25 days ago
SEAMS: Simulation Environment for VHDL-AMS
VHDL-AMS is an Analog and Mixed-Signal extension to the Very High Speed Integrated Circuit Hardware Description Language (VHDL). With the standardization of VHDL-AMS, capable and ...
Peter Frey, Kathiresan Nellayappan, Vasudevan Sahn...
FDL
2007
IEEE
14 years 5 months ago
An Extension to VHDL-AMS for AMS Systems with Partial Differential Equations
Abstract This paper proposes VHDL-AMS syntax extensions that enable descriptions of AMS systems with partial differential equations. We named the extended language VHDL-AMSP. An im...
Leran Wang, Chenxu Zhao, Tom J. Kazmierski