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HIPEAC
2009
Springer
14 years 3 months ago
HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic
Abstract. Exposing more instruction-level parallelism in out-of-order superscalar processors requires increasing the number of dynamic in-flight instructions. However, large instru...
Suriya Subramanian, Kathryn S. McKinley
ISHPC
2003
Springer
14 years 4 months ago
A Simple Low-Energy Instruction Wakeup Mechanism
Instruction issue consumes a large amount of energy in out of order processors, largely in the wakeup logic. Proposed solutions to the problem require prediction or additional hard...
Marco A. Ramírez, Adrián Cristal, Al...
HPCA
2004
IEEE
14 years 11 months ago
Reducing the Scheduling Critical Cycle Using Wakeup Prediction
For highest performance, a modern microprocessor must be able to determine if an instruction is ready in the same cycle in which it is to be selected for execution. This creates a...
Todd E. Ehrhart, Sanjay J. Patel