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Lectures on VLSI and Integrated Circuit Design | |
scale.engin.brown.edu VLSI (Very Large Scale Integration) CMOS (Complementary Metal Oxide Semiconductor) technology is the main driver of our digital revolution. The goals of these l... | |
1962 views 81 votes |
Lectures on reconfigurable computing | |
scale.engin.brown.edu Driven by recent innovations in Field-Programmable Gate Arrays (FPGAs), reconfigurable computing offers unique ways to accelerate key algorithms. FPGAs offer a ... | |
1005 views 80 votes |
Future Directions in Computing | |
scale.engin.brown.edu Silicon-based electronics is the foundation of computing devices. The computer industry is reaching an important milestone, where physical limits arising from u... | |
889 views 72 votes |
Within-die Process Variations: How Accurately can They Be Statistically Modeled? | |
scale.engin.brown.edu Within-die process variations arise during integrated circuit (IC) fabrication in the sub-100nm regime. These variations are of paramount concern as they deviat... | |
576 views 95 votes |
Frequency and voltage planning for multi-core processors under thermal constraints | |
ic.engin.brown.edu — Clock frequency and transistor density increases have resulted in elevated chip temperatures. In order to meet temperature constraints while still exploitin... | |
420 views 74 votes |
Consistent runtime thermal prediction and control through workload phase detection | |
295 views 73 votes |
Spectral techniques for high-resolution thermal characterization with limited sensor data | |
ic.engin.brown.edu Elevated chip temperatures are true limiters to the scalability of computing systems. Excessive runtime thermal variations compromise the performance and relia... | |
274 views 69 votes |
Central vs. distributed dynamic thermal management for multi-core processors: which one is better? | |
262 views 84 votes |
APlace: a general analytic placement framework | |
ic.engin.brown.edu We streamline and extend APlace, the general analytic placement engine based on ideas of Naylor et al. [7] and described in [3, 4, 5]. Previous work explored t... | |
249 views 53 votes |
Thermal monitoring of real processors: techniques for sensor allocation and full characterization | |
216 views 72 votes |
Hardware libraries: An architecture for economic acceleration in soft multi-core environments | |
www.eecs.umich.edu In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in t... | |
205 views 47 votes |
High-performance, cost-effective heterogeneous 3D FPGA architectures | |
ic.engin.brown.edu In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias ... | |
189 views 52 votes |
A semi-persistent clustering technique for VLSI circuit placement | |
ic.engin.brown.edu Placement is a critical component of today's physical synthesis flow with tremendous impact on the final performance of VLSI designs. However, it accounts for ... | |
188 views 52 votes |
On the Relation between SAT and BDDs for Equivalence Checking | |
ic.engin.brown.edu State-of-the-art verification tools are based on efficient operations on Boolean formulas. Traditional manipulation techniques are based on Binary Decision Dia... | |
175 views 79 votes |
Engineering a scalable placement heuristic for DNA probe arrays | |
173 views 35 votes |
Evaluation of Placement Techniques for DNA Probe Array Layout | |
ic.engin.brown.edu DNA probe arrays have emerged as a core genomic technology that enables cost-effective gene expression monitoring, mutation detection, single nucleotide polymo... | |
170 views 45 votes |
Analyzing the impact of process variations on parametric measurements: Novel models and applications | |
ic.engin.brown.edu Abstract—In this paper we propose a novel statistical framework to model the impact of process variations on semiconductor circuits through the use of process... | |
167 views 50 votes |
On-Line Adjustable Buffering for Runtime Power Reduction | |
ic.engin.brown.edu We present a novel technique to exploit the power-performance tradeoff. The technique can be used stand-alone or in conjunction with dynamic voltage scaling, ... | |
165 views 47 votes |
Power-aware placement | |
ic.engin.brown.edu Lowering power is one of the greatest challenges facing the IC industry today. We present a power-aware placement method that simultaneously performs (1) activ... | |
161 views 40 votes |
Strategies for improving the parametric yield and profits of 3D ICs | |
158 views 51 votes |
Effective linear programming based placement methods | |
ic.engin.brown.edu Linear programming (LP) based methods are attractive for solving the placement problem because of their ability to model Half-Perimeter Wirelength (HPWL) and t... | |
158 views 48 votes |
Evaluation of placer suboptimality via zero-change netlist transformations | |
ic.engin.brown.edu In this paper we introduce the concept of zero-change transformations to quantify the suboptimality of existing placers. Given a netlist and its placement from... | |
153 views 50 votes |
Architecture and details of a high quality, large-scale analytical placer | |
ic.engin.brown.edu Modern design requirements have brought additional complexities to netlists and layouts. Millions of components, whitespace resources, and fixed/movable block... | |
151 views 50 votes |
Combinatorial group testing methods for the BIST diagnosis problem | |
vlsicad.ucsd.edu — We examine an abstract formulation of BIST diagnosis in digital logic systems. The BIST diagnosis problem has applications that include identification of e... | |
151 views 48 votes |
Boosting: Min-Cut Placement with Improved Signal Delay | |
ic.engin.brown.edu In this work we improve top-down min-cut placers in the context of timing closure. Using the concept of boosting factors, we adjust net weights according to ne... | |
151 views 67 votes |
A tale of two nets: studies of wirelength progression in physical design | |
ic.engin.brown.edu At every stage in physical design, engineers are faced with many different objectives and tools to develop, optimize, and evaluate their design. Each choice o... | |
149 views 52 votes |
Design Flow Enhancements for DNA Arrays | |
vlsicad.ucsd.edu DNA probe arrays have recently emerged as one of the core genomic technologies. Exploiting analogies between manufacturing processes for DNA arrays and for VLS... | |
147 views 45 votes |
Using circuit structural analysis techniques for networks in systems biology | |
147 views 29 votes |
Placement feedback: a concept and method for better min-cut placements | |
ic.engin.brown.edu The advent of strong multi-level partitioners has made topdown min-cut placers a favored choice for modern placer implementations. We examine terminal propagat... | |
139 views 43 votes |
Reducing Test Application Time Through Test Data Mutation Encoding | |
ic.engin.brown.edu In this paper we propose a new compression algorithm geared to reduce the time needed to test scan-based designs. Our scheme compresses the test vector set by ... | |
135 views 45 votes |
Intrinsic shortest path length: a new, accurate a priori wirelength estimator | |
vlsicad.ucsd.edu A priori wirelength estimation is concerned with predicting various wirelength characteristics before placement. In this work we propose a novel, accurate esti... | |
122 views 41 votes |