90%
us
1University of Iowa02 Jun 11
tr
1Namik Kemal University09 Jun 11
us
340United States
un
83
cn
27China
ru
13Russian Federation
tr
7Turkey
in
5India
nl
4Netherlands
vn
3Vietnam
de
2Germany
se
2Sweden
jp
1Japan
it
1Italy
rs
1Serbia
Lectures on VLSI and Integrated Circuit Design
Lectures on VLSI and Integrated Circuit Design
scale.engin.brown.edu
VLSI (Very Large Scale Integration) CMOS (Complementary Metal Oxide Semiconductor) technology is the main driver of our digital revolution. The goals of these l...
1962 views   81 votes
Sherief Reda
Lectures on reconfigurable computing
Lectures on reconfigurable computing
scale.engin.brown.edu
Driven by recent innovations in Field-Programmable Gate Arrays (FPGAs), reconfigurable computing offers unique ways to accelerate key algorithms. FPGAs offer a ...
1005 views   80 votes
Sherief Reda
Future Directions in Computing
Future Directions in Computing
scale.engin.brown.edu
Silicon-based electronics is the foundation of computing devices. The computer industry is reaching an important milestone, where physical limits arising from u...
889 views   72 votes
Sherief Reda
Within-die Process Variations: How Accurately can They Be Statistically Modeled?
Within-die Process Variations: How Accurately can They Be Statistically Modeled?
scale.engin.brown.edu
Within-die process variations arise during integrated circuit (IC) fabrication in the sub-100nm regime. These variations are of paramount concern as they deviat...
576 views   95 votes
Brendan Hargreaves, Henrik Hult, Sherief Reda
Frequency and voltage planning for multi-core processors under thermal constraints
Frequency and voltage planning for multi-core processors under thermal constraints
ic.engin.brown.edu
— Clock frequency and transistor density increases have resulted in elevated chip temperatures. In order to meet temperature constraints while still exploitin...
420 views   74 votes
IEEE Michael Kadin, Sherief Reda
Spectral techniques for high-resolution thermal characterization with limited sensor data
Spectral techniques for high-resolution thermal characterization with limited sensor data
ic.engin.brown.edu
Elevated chip temperatures are true limiters to the scalability of computing systems. Excessive runtime thermal variations compromise the performance and relia...
274 views   69 votes
ACM Ryan Cochran, Sherief Reda
APlace: a general analytic placement framework
APlace: a general analytic placement framework
ic.engin.brown.edu
We streamline and extend APlace, the general analytic placement engine based on ideas of Naylor et al. [7] and described in [3, 4, 5]. Previous work explored t...
249 views   53 votes
ACM Andrew B. Kahng, Sherief Reda, Qinke Wang
Thermal monitoring of real processors: techniques for sensor allocation and full characterization
Thermal monitoring of real processors: techniques for sensor allocation and full characterization
216 views   72 votes
ACM Abdullah Nazma Nowroz, Ryan Cochran, Sherief Reda
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
www.eecs.umich.edu
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in t...
205 views   47 votes
IEEE David Meisner, Sherief Reda
High-performance, cost-effective heterogeneous 3D FPGA architectures
High-performance, cost-effective heterogeneous 3D FPGA architectures
ic.engin.brown.edu
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias ...
189 views   52 votes
IEEE Roto Le, Sherief Reda, R. Iris Bahar
A semi-persistent clustering technique for VLSI circuit placement
A semi-persistent clustering technique for VLSI circuit placement
ic.engin.brown.edu
Placement is a critical component of today's physical synthesis flow with tremendous impact on the final performance of VLSI designs. However, it accounts for ...
188 views   52 votes
ACM Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia
On the Relation between SAT and BDDs for Equivalence Checking
On the Relation between SAT and BDDs for Equivalence Checking
ic.engin.brown.edu
State-of-the-art verification tools are based on efficient operations on Boolean formulas. Traditional manipulation techniques are based on Binary Decision Dia...
175 views   79 votes
IEEE Sherief Reda, Rolf Drechsler, Alex Orailoglu
Engineering a scalable placement heuristic for DNA probe arrays
Engineering a scalable placement heuristic for DNA probe arrays
173 views   35 votes
Springer Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky
Evaluation of Placement Techniques for DNA Probe Array Layout
Evaluation of Placement Techniques for DNA Probe Array Layout
ic.engin.brown.edu
DNA probe arrays have emerged as a core genomic technology that enables cost-effective gene expression monitoring, mutation detection, single nucleotide polymo...
170 views   45 votes
IEEE Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky
Analyzing the impact of process variations on parametric measurements: Novel models and applications
Analyzing the impact of process variations on parametric measurements: Novel models and applications
ic.engin.brown.edu
Abstract—In this paper we propose a novel statistical framework to model the impact of process variations on semiconductor circuits through the use of process...
167 views   50 votes
IEEE Sherief Reda, Sani R. Nassif
On-Line Adjustable Buffering for Runtime Power Reduction
On-Line Adjustable Buffering for Runtime Power Reduction
ic.engin.brown.edu
We present a novel technique to exploit the power-performance tradeoff. The technique can be used stand-alone or in conjunction with dynamic voltage scaling, ...
165 views   47 votes
IEEE Andrew B. Kahng, Sherief Reda, Puneet Sharma
Power-aware placement
Power-aware placement
ic.engin.brown.edu
Lowering power is one of the greatest challenges facing the IC industry today. We present a power-aware placement method that simultaneously performs (1) activ...
161 views   40 votes
ACM Yongseok Cheon, Pei-Hsin Ho, Andrew B. Kahng, Sherief Reda, Qinke Wang
Strategies for improving the parametric yield and profits of 3D ICs
Strategies for improving the parametric yield and profits of 3D ICs
158 views   51 votes
IEEE Cesare Ferri, Sherief Reda, R. Iris Bahar
Effective linear programming based placement methods
Effective linear programming based placement methods
ic.engin.brown.edu
Linear programming (LP) based methods are attractive for solving the placement problem because of their ability to model Half-Perimeter Wirelength (HPWL) and t...
158 views   48 votes
ACM Sherief Reda, Amit Chowdhary
Evaluation of placer suboptimality via zero-change netlist transformations
Evaluation of placer suboptimality via zero-change netlist transformations
ic.engin.brown.edu
In this paper we introduce the concept of zero-change transformations to quantify the suboptimality of existing placers. Given a netlist and its placement from...
153 views   50 votes
ACM Andrew B. Kahng, Sherief Reda
Architecture and details of a high quality, large-scale analytical placer
Architecture and details of a high quality, large-scale analytical placer
ic.engin.brown.edu
Modern design requirements have brought additional complexities to netlists and layouts. Millions of components, whitespace resources, and fixed/movable block...
151 views   50 votes
IEEE Andrew B. Kahng, Sherief Reda, Qinke Wang
Combinatorial group testing methods for the BIST diagnosis problem
Combinatorial group testing methods for the BIST diagnosis problem
vlsicad.ucsd.edu
— We examine an abstract formulation of BIST diagnosis in digital logic systems. The BIST diagnosis problem has applications that include identification of e...
151 views   48 votes
ACM Andrew B. Kahng, Sherief Reda
Boosting: Min-Cut Placement with Improved Signal Delay
Boosting: Min-Cut Placement with Improved Signal Delay
ic.engin.brown.edu
In this work we improve top-down min-cut placers in the context of timing closure. Using the concept of boosting factors, we adjust net weights according to ne...
151 views   67 votes
IEEE Andrew B. Kahng, Igor L. Markov, Sherief Reda
A tale of two nets: studies of wirelength progression in physical design
A tale of two nets: studies of wirelength progression in physical design
ic.engin.brown.edu
At every stage in physical design, engineers are faced with many different objectives and tools to develop, optimize, and evaluate their design. Each choice o...
149 views   52 votes
ACM Andrew B. Kahng, Sherief Reda
Design Flow Enhancements for DNA Arrays
Design Flow Enhancements for DNA Arrays
vlsicad.ucsd.edu
DNA probe arrays have recently emerged as one of the core genomic technologies. Exploiting analogies between manufacturing processes for DNA arrays and for VLS...
147 views   45 votes
IEEE Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky
Placement feedback: a concept and method for better min-cut placements
Placement feedback: a concept and method for better min-cut placements
ic.engin.brown.edu
The advent of strong multi-level partitioners has made topdown min-cut placers a favored choice for modern placer implementations. We examine terminal propagat...
139 views   43 votes
ACM Andrew B. Kahng, Sherief Reda
Reducing Test Application Time Through Test Data Mutation Encoding
Reducing Test Application Time Through Test Data Mutation Encoding
ic.engin.brown.edu
In this paper we propose a new compression algorithm geared to reduce the time needed to test scan-based designs. Our scheme compresses the test vector set by ...
135 views   45 votes
IEEE Sherief Reda, Alex Orailoglu
Intrinsic shortest path length: a new, accurate a priori wirelength estimator
Intrinsic shortest path length: a new, accurate a priori wirelength estimator
vlsicad.ucsd.edu
A priori wirelength estimation is concerned with predicting various wirelength characteristics before placement. In this work we propose a novel, accurate esti...
122 views   41 votes
IEEE Andrew B. Kahng, Sherief Reda
about sreda
Powered by
sciweavers