CDES 2006 - PDF Preprint Papers

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CDES
2006

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Round-Robin Arbiter Design

13 years 6 months ago

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- Round-robin has been used as a fair (non starvation) scheduling policy in many computer applications. This paper presents a novel hardware design of a round-robin arbiter without...

Jinming Ge

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Id	Views	Title	Status

1	249	Round-Robin Arbiter Design	claim
2	240	Design of Low Power 4-Tap 8-Bit Adiabatic FIR Filter	claim
3	184	Compilation for Future Nanocomputer Architectures	claim
4	158	A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs	claim
5	149	Crosstalk at the Dynamic Node of Domino CMOS Circuits	claim
6	146	ANN-Based Spiral Inductor Parameter Extraction and Layout Re-Design	claim
7	136	Using Task Recomputation During Application Mapping in Parallel Embedded Architectures	claim
8	136	CMOL FPGA circuits	claim
9	118	New DSP Benchmark based on Selectable Mode Vocoder (SMV)	claim
10	118	Improving the System Performance by a Dynamic File Prediction Model	claim
11	112	A New Processor Architecture with a New Program Driving Method	claim
12	108	RHT: A Context-Based Return Address Predictor	claim
13	108	MolML: An Abstract Scripting Language for Assembly of Mechanical Nanocomputer Architectures	claim
14	107	An Algorithm for Yield Improvement via Local Positioning and Resizing	claim
15	106	Reducing Memory References for FFT Calculation	claim
16	106	A Novel Essential Prime Implicant Identification Method for Exact Direct Cover Logic Minimization	claim
17	101	Hybrid Error-Detection Approach with No Detection Latency for High-Performance Microprocessors	claim
18	100	Integrity and Integration Issues for Nano-Tube Based Interconnect Systems	claim
19	100	Towards a Nanoscale Artificial Cortex	claim
20	99	Realization of Digital Fuzzy Operations Using Multi-Valued Fredkin Gates	claim
21	99	Teraflop Computing for Nanoscience	claim
22	98	Instruction Fetch Energy Reduction Using Forward-Branch Bufferable Innermost Loop Buffer	claim
23	97	Protein Secondary Structure Prediction Accuracy versus Reduction Methods	claim
24	96	Bandwidth-Friendly Cache Hierarchy	claim
25	96	Semi-Contiguous Memory Allocation for Efficient Sequential-Access	claim
26	91	Survey and Evaluation of Low-Power Flip-Flops	claim
27	89	Autonomous Instruction Memory Equipped with Dynamic Branch Handling Capability	claim
28	87	A Configuration Concept for a Massively Parallel FPGA Architecture	claim
29	84	Simulation of a Turing Machine using EndoII Splicing Rules	claim
30	80	Communicating Distributed H systems with Simple Splicing Rules	claim
31	78	The Impact of Cache Organization in Optimizing Microprocessor Power Consumption	claim
32	76	Novel NAND and AND Gate Using DNA Ligation and Two Transistors Implementations	claim
33	74	Zero Detect-Based Low Power Registers File Access	claim
34	62	On the Management of Object Interrelationships	claim

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