DSD 2008 - PDF Preprint Papers

DSD 2008 Euromicro Symposium on Digital Systems Design

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DSD
2008
IEEE

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How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design

13 years 11 months ago

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Ultra low power digital systems are key for any future wireless sensor nodes but also inside nomadic embedded systems (such as inside the digital front end of software defined rad...

Giacomo Paci, A. Nackaerts, Francky Catthoor, Luca...

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Id	Views	Title	Status

1	187	How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design	claim
2	168	Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture	claim
3	166	Pearson - based Analysis of Positioning Error Distribution in Wireless Sensor Networks	claim
4	165	Application Analysis for Parallel Processing	claim
5	147	A Low-Cost Cache Coherence Verification Method for Snooping Systems	claim
6	145	Formulating MITF for a Multicore Processor with SEU Tolerance	claim
7	139	Revisiting the Cache Effect on Multicore Multithreaded Network Processors	claim
8	139	Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration	claim
9	136	Network Interface Sharing Techniques for Area Optimized NoC Architectures	claim
10	136	Flexible Baseband Architectures for Future Wireless Systems	claim
11	131	PUFFIN: A Novel Compact Block Cipher Targeted to Embedded Digital Systems	claim
12	130	On the Need for Passive Monitoring in Sensor Networks	claim
13	127	Measurement, Analysis and Modeling of RTOS System Calls Timing	claim
14	125	On the Complexity of Error Detection Functions for Redundant Residue Number Systems	claim
15	124	A Modular Approach to Model Heterogeneous MPSoC at Cycle Level	claim
16	121	A Parallel and Modular Architecture for 802.16e LDPC Codes	claim
17	115	An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA	claim
18	115	Reliable Data Transmission over Simple Wireless Channels: A Case Study	claim
19	110	VLSI Implementation of a Cryptography-Oriented Reconfigurable Array	claim
20	108	Reducing Leakage through Filter Cache	claim
21	107	Acceleration of Smith-Waterman using Recursive Variable Expansion	claim
22	106	Leveraging Data Promotion for Low Power D-NUCA Caches	claim
23	104	CART: Communication-Aware Routing Technique for Application-Specific NoCs	claim
24	104	A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures	claim
25	96	On Lookup Table Cascade-Based Realizations of Arbiters	claim
26	95	Programmable Numerical Function Generators for Two-Variable Functions	claim
27	94	Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip	claim
28	91	A New Rounding Algorithm for Variable Latency Division and Square Root Implementations	claim
29	85	TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path	claim
30	84	A Hardware Implementation of CURUPIRA Block Cipher for Wireless Sensors	claim
31	79	Digital Systems Architectures Based on On-line Checkers	claim

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