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ISCAS 2003 International Symposium on Circuits and Systems

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ISCAS
2003
IEEE

345views Hardware» more ISCAS 2003»

An efficient blood vessel detection algorithm for retinal images using local entropy thresholding

13 years 10 months ago

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This paper presents an efﬁcient method for automatic detection and extraction of blood vessels in retinal images. Speciﬁcally, we also delineate vascular intersections/crossov...

Thitiporn Chanwimaluang, Guoliang Fan

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Id	Views	Title	Status

1	345	An efficient blood vessel detection algorithm for retinal images using local entropy thresholding	claim
2	331	Design of ultra high-speed CMOS CML buffers and latches	claim
3	279	A high speed low input current low voltage CMOS current comparator	claim
4	257	A DNA-based, biomolecular cryptography design	claim
5	235	Enhanced chaotic image encryption algorithm based on Baker's map	claim
6	201	A regularized simultaneous autoregressive model for texture classification	claim
7	189	Bio-inspired optical flow circuits for the visual guidance of micro air vehicles	claim
8	185	A semi-fragile object based video authentication system	claim
9	183	Polyphase IIR filter banks for subband adaptive echo cancellation applications	claim
10	175	Analysis of timing jitter in ring oscillators due to power supply noise	claim
11	172	Efficient symbol synchronization techniques using variable FIR or IIR interpolation filters	claim
12	172	Performance modeling of resonant tunneling based RAMs	claim
13	169	Efficient implementation of complex exponentially-modulated filter banks	claim
14	169	One class of transfer functions with monotonic step response	claim
15	168	Hardware-oriented optimization and block-level architecture design for MPEG-4 FGS encoder	claim
16	167	The multi-level paradigm for distributed fault detection in networks with unreliable processors	claim
17	162	Content based error detection and concealment for image transmission over wireless channel	claim
18	156	GNOMES: a testbed for low power heterogeneous wireless sensor networks	claim
19	153	A VLSI model of range-tuned neurons in the bat echolocation system	claim
20	150	Accurate rise time and overshoots estimation in RLC interconnects	claim
21	148	Hybrid neural network architecture for age identification of ancient Kannada scripts	claim
22	147	Parameterized and low power DSP core for embedded systems	claim
23	145	Automatic moving object extraction in MPEG video	claim
24	144	A flexible global readout architecture for an analogue SIMD vision chip	claim
25	142	The CMOS/nano interface from a circuits perspective	claim
26	140	On use of averaging in FxLMS algorithm for single-channel feedforward ANC systems	claim
27	139	Development of an AA size energy transducer with micro resonators	claim
28	139	Mixed-signal gradient flow bearing estimation	claim
29	139	A subspace method for channel estimation of multi-user multi-antenna OFDM system	claim
30	137	Motion field interpolation for frame rate conversion	claim
31	135	Formal verification of LTL formulas for SystemC designs	claim
32	135	Stability and stabilisation of 2D discrete linear systems with multiple delays	claim
33	134	A hybrid system for automatic fingerprint identification	claim
34	134	Analog and mixed signal modelling with SystemC-AMS	claim
35	133	A mutual information approach to articulated object tracking	claim
36	132	Characterization of a simple communication network using Legendre transform	claim
37	131	Process variation dimension reduction based on SVD	claim
38	129	SONICmole: a debugging environment for the UltraSONIC reconfigurable computer	claim
39	128	A semi-Gray encoding algorithm for low-power state assignment	claim
40	128	Robust digital image-in-image watermarking algorithm using the fast Hadamard transform	claim
41	128	Placement with symmetry constraints for analog layout using red-black trees	claim
42	128	Phase noise improvement in fractional-N synthesizer with 90/spl deg/ phase shift lock	claim
43	127	A wide-band current-mode OTA-based analog multiplier-divider	claim
44	127	Use of state trajectory prediction in hysteresis control for achieving fast transient response of the buck converter	claim
45	127	Nonuniform sampling driver design for optimal ADC utilization	claim
46	126	Bit rate optimized time-domain equalizers for DMT systems	claim
47	126	Low power block based FIR filtering cores	claim
48	126	High-speed processor for quantum-computing emulation and its applications	claim
49	126	A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems	claim
50	126	Rate distortion optimization in the scalable video coding	claim
51	125	Low noise amplifier design for ultra-wideband radio	claim
52	125	A blind watermarking technique for multiple watermarks	claim
53	124	Convergent transfer subgraph characterization and computation	claim
54	124	An active leakage-injection scheme applied to low-voltage SRAMs	claim
55	124	Analysis of output ripple in multi-phase clocked charge pumps	claim
56	124	Improving the filter bank of a classic speech feature extraction algorithm	claim
57	123	Fast prototyping of reconfigurable architectures from a C program	claim
58	123	Classification of power system faults using wavelet transforms and probabilistic neural networks	claim
59	122	Reducing the number of variable movements in exact BDD minimization	claim
60	122	High-efficiency electronic transformer for low-voltage halogen lamp	claim
61	122	Toward a wireless optical communication link between two small unmanned aerial vehicles	claim
62	122	Bulk carbon nanotube as thermal sensing and electronic circuit elements	claim
63	121	Dominant color image retrieval using merged histogram	claim
64	120	Combining adaptive smoothing and decision-directed channel estimation schemes for OFDM WLAN systems	claim
65	120	Subgridding method for speeding up FD-TLM circuit simulation	claim
66	119	Area-time optimal adder with relative placement generator	claim
67	119	Modeling skin effect with reduced decoupled R-L circuits	claim
68	119	Electrical characteristics of multi-layer power distribution grids	claim
69	119	Simulated evolution algorithm for multiobjective VLSI netlist bi-partitioning	claim
70	118	Providing flexibility in a convolutional encoder	claim
71	118	Embedded reconfigurable array targeting motion estimation applications	claim
72	118	SoC design integration by using automatic interconnection rectification	claim
73	117	Learning temporal correlations in biologically-inspired aVLSI	claim
74	116	Effective hardware-oriented technique for the rate control of JPEG2000 encoding	claim
75	116	Using FPGAs to solve the Hamiltonian cycle problem	claim
76	116	Channel compensation of modulation spectral features	claim
77	115	An efficient color compensation scheme for skin color segmentation	claim
78	114	On the hardware implementations of the SHA-2 (256, 384, 512) hash functions	claim
79	113	Tile-graph-based power planning	claim
80	113	Analog-decoder experiments with subthreshold CMOS soft-gates	claim
81	113	Optimum word length allocation for multipliers of integer DCT	claim
82	113	Capacitively coupled multiple resonance networks	claim
83	112	A novel de-interlacing technique based on phase plane correlation motion estimation	claim
84	112	Energy-balancing strategies for wireless sensor networks	claim
85	112	A low-power adaptive integrate-and-fire neuron circuit	claim
86	112	Distributed neurochemical sensing: in vitro experiments	claim
87	112	Architectures for function evaluation on FPGAs	claim
88	111	A 2048 complex point FFT processor using a novel data scaling approach	claim
89	111	Bit allocation for progressive fine granularity scalable video coding with temporal-SNR scalabilities	claim
90	111	An efficient transistor optimizer for custom circuits	claim
91	110	A modular test structure for CMOS mismatch characterization	claim
92	110	Interconnect modeling and sensitivity analysis using adjoint networks reduction technique	claim
93	110	Active subset selection approach to nonlinear modeling of ECG data	claim
94	110	Chaos in cross-coupled BVP oscillators	claim
95	110	Relations between spatio-temporal phenomena and eigenvalues in mutually coupled CNNs	claim
96	109	Rate control for advance video coding (AVC) standard	claim
97	108	Applications of nonlinear dynamics to the turbo decoding algorithm	claim
98	108	Co-existence of chaos-based and conventional digital communication systems	claim
99	108	An extended radix-based digital calibration technique for multi-stage ADC	claim
100	108	View-dependent transmission of 3-D normal meshes	claim
101	108	Usable speech measures and their fusion	claim
102	107	A coding method for 123 decision diagram pass transistor logic circuit synthesis	claim
103	107	Automatic synchronization of speech transcript and slides in presentation	claim
104	107	Synthesis of a pulse-forming reactance network to shape a delayed quasi-rectangular pulse	claim
105	107	On chip Gaussian processing for high resolution CMOS image sensors	claim
106	107	Optimal adaptive parallel diagnosis for arrays	claim
107	106	5th order electro-thermal multi-tone Volterra simulator with component-level output	claim
108	106	Content based photograph slide show with incidental music	claim
109	106	Design of a digital reaction-diffusion system for restoring blurred fingerprint images	claim
110	106	Secure data hiding in binary document images for authentication	claim
111	106	A neuromorphic sound localizer for a smart MEMS system	claim
112	106	Resource adaptation based on MPEG-21 usage environment descriptions	claim
113	105	Algorithmic partial analog-to-digital conversion in mixed-signal array processors	claim
114	104	Real-time scheduling on scalable media stream delivery	claim
115	104	Micromachined piezoresistive tactile sensor array fabricated by bulk-etched MUMPs process	claim
116	104	Study and simulation of CMOS LC oscillator phase noise and jitter	claim
117	104	Synchronization of a network of intermittently coupled capacitor circuits	claim
118	103	An ILP-based scheduling scheme for energy efficient high performance datapath synthesis	claim
119	103	A massively scaleable decoder architecture for low-density parity-check codes	claim
120	103	Low delay rate-control in video transcoding	claim
121	103	Low-noise biasing of voltage-controlled oscillators by means of resonant inductive degeneration	claim
122	102	Analog wavelet transform employing dynamic translinear circuits for cardiac signal characterization	claim
123	102	A time-series processor for sonar mapping and novelty detection	claim
124	102	A deterministic dynamic element matching approach to ADC testing	claim
125	102	Adaptivity figures of merit and K-rail diagrams - comprehensive performance characterization of low-noise amplifiers and voltage-controlled oscillators	claim
126	102	Bifurcation analysis of a power-factor-correction boost converter: uncovering fast-scale instability	claim
127	101	Controlling chaos via second-order sliding modes	claim
128	101	A 5th order Volterra study of a 30W LDMOS power amplifier	claim
129	100	Area-effective FIR filter design for multiplier-less implementation	claim
130	100	Wire-speed traffic management in Ethernet switches	claim
131	99	Time-delay modelling for multi-layer power systems	claim
132	99	Continuous-time, frequency translating, bandpass delta-sigma modulator	claim
133	99	Analysis of a simple A/D converter with a trapping window	claim
134	99	New hyperbolic source density models for blind source recovery score functions	claim
135	99	Optimization of shield structures in analog integrated circuits	claim
136	98	Dynamic operand transformation for low-power multiplier-accumulator design	claim
137	98	Minimum selection GSC and adaptive low-power rake combining scheme	claim
138	98	Multitasking in hardware-software codesign for reconfigurable computer	claim
139	97	Watermark re-synchronization using log-polar mapping of image autocorrelation	claim
140	97	An 8-bit, 1mW successive approximation ADC in SOI CMOS	claim
141	97	A multi-level static memory cell	claim
142	97	Optimal design of FIR frequency-response-masking filters using second-order cone programming	claim
143	97	The integer MDCT and its application in the MPEG layer III audio	claim
144	97	A CMOS neural oscillator using negative resistance	claim
145	97	A 40 GHz modified-Colpitts voltage controlled oscillator with increased tuning range	claim
146	97	A fast and low power CMOS sensor for optical tracking	claim
147	96	High-speed VLSI architecture for parallel Reed-Solomon decoder	claim
148	96	Wavelet-transform-based strategy for generating new Chinese fonts	claim
149	96	A wide linear range low-voltage transconductor	claim
150	96	Interface design approach for system on chip based on configuration	claim
151	96	A novel improvement technique for high-level test synthesis	claim
152	95	Analog representation and digital implementation of OFDM systems	claim
153	95	Information embedding in JPEG-2000 compressed images	claim
154	94	PODEA: Power delivery efficient analysis with realizable model reduction	claim
155	93	Lossless non-arbitrated address-event coding	claim
156	93	Design of chaotic spread-spectrum sequences with good correlation properties for DS/CDMA	claim
157	93	An ultra low-power dynamic translinear cardiac sense amplifier for pacemakers	claim
158	93	A rescheduling and fast pipeline VLSI architecture for lifting-based discrete wavelet transform	claim
159	93	A hybrid delta-sigma modulator with adaptive calibration	claim
160	93	Shift-accumulator ALU centric JPEG2000 5/3 lifting based discrete wavelet transform architecture	claim
161	93	Concept of transformer-feedback degeneration of low-noise amplifiers	claim
162	93	A low power charge sharing ROM using dummy bit lines	claim
163	92	Multi-server optimal bandwidth monitoring for QoS based multimedia delivery	claim
164	92	Motion adaptive de-interlacing by horizontal motion detection and enhanced ELA processing	claim
165	92	Evidence updating in a heterogeneous sensor environment	claim
166	92	Compact integrated transconductance amplifier circuit for temporal differentiation	claim
167	91	Design of ultraspherical windows with prescribed spectral characteristics	claim
168	91	Variable delay ripple carry adder with carry chain interrupt detection	claim
169	91	Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity	claim
170	91	Real-time implementation of H.263+ using TI TMS320c6201 digital signal processor	claim
171	91	SDP for multi-criterion QMF bank design	claim
172	90	A 5-GHz self-calibrated I/Q clock generator using a quadrature LC-VCO	claim
173	90	Joint time delay and pitch estimation for speaker localization	claim
174	90	"Intermittent" chaos and subharmonics in switching power supplies	claim
175	90	An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication	claim
176	90	A reduction technique of large scale RCG interconnects in complex frequency domain	claim
177	89	Thin film PIN photodiodes for optoelectronic silicon on sapphire CMOS	claim
178	89	Synthesizing checkers for on-line verification of System-on-Chip designs	claim
179	89	Nonautonomous pulse-driven chaotic oscillator based on Chua's circuit	claim
180	89	DCT-based video frame-skipping transcoder	claim
181	89	A time-interleaved switched-capacitor band-pass delta-sigma modulator	claim
182	89	Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output	claim
183	89	Systematic test program generation for SoC testing using embedded processor	claim
184	89	Performance evaluation of optimal DMT transceivers for ADSL application	claim
185	88	Cell clinics for bioelectronic interface with single cells	claim
186	88	Power dissipation limits and large margin in wireless sensors	claim
187	88	Periodic orbits and bifurcations in one-dimensional arrays of Chua's circuits	claim
188	88	Load cell response correction using analog adaptive techniques	claim
189	88	A small analog VLSI inner hair cell model	claim
190	87	M-channel lifting-based design of paraunitary and biorthogonal filter banks with structural regularity	claim
191	87	Multicast video synchronization via MPEG-4 FGS/XML representation	claim
192	86	Hardware implementation of evolutionary digital filters	claim
193	86	Performance characteristics of an ultra-low power VCO	claim
194	86	PWL approximation of dynamical systems: an example	claim
195	85	Exploiting reconfigurability for low-power control of embedded processors	claim
196	85	A robust global motion estimation scheme for sprite coding	claim
197	85	Application of MEMS technologies to nanodevices	claim
198	85	New designs of frequency selective FIR digital filters	claim
199	85	Area-efficient memory-based architecture for FFT processing	claim
200	84	A logic-aware layout methodology to enhance the noise immunity of domino circuits	claim
201	84	A sigma-delta based open-loop frequency modulator	claim
202	84	CMOS optical receiver chipset for gigabit Ethernet applications	claim
203	84	Performance optimization for motion compensated 2D wavelet video compression techniques	claim
204	84	The fault detection of cross-check test scheme for infrared FPA	claim
205	83	Optimization of power consumption for an ARM7-based multimedia handheld device	claim
206	83	A high-resolution and fast-conversion time-to-digital converter	claim
207	83	Low-noise low-power allpole active-RC filters minimizing resistor level	claim
208	83	Stable high-order delta-sigma DACS	claim
209	83	Application of wavelet transform to steady-state approximation of power electronics waveforms	claim
210	83	An Integrated Framework of Design Optimization and Space Minimization for DSP applications	claim
211	82	On the feasibility of application of class E RF power amplifiers in UMTS	claim
212	82	A hyperchaotic circuit family including a dependent switched capacitor	claim
213	81	Limits in FIR subband beamforming for spatially spread near-field speech sources	claim
214	80	Generation of homoclinic oscillation in coupled Chua's oscillators	claim
215	80	A system-on-chip featuring variable bus architecture and enhanced video coprocessors for MPEG-4 multimedia applications	claim
216	80	Pairing and ordering to reduce hardware complexity in cascade form filter design	claim
217	80	Clock recovery in high-speed multilevel serial links	claim
218	80	The tau-cell: a new method for the implementation of arbitrary differential equations	claim
219	79	A low-power CMOS complex filter for Bluetooth with frequency tuning	claim
220	79	Movement of small amplitude parts in a coupled chaotic system	claim
221	79	Peak-to-average power-ratio reduction via channel hopping for downlink CDMA systems	claim
222	79	Computation reduction in cascaded DCT-domain video downscaling transcoding	claim
223	79	Efficient interconnect modeling by Finite Difference Quadrature methods	claim
224	79	Design of a low power psycho-acoustic model co-processor for MPEG-2/4 AAC LC stereo encoder	claim
225	78	SLAP: a system for the detection and correction of pronunciation for second language acquisition	claim
226	78	A silicon retina system that calculates direction of motion	claim
227	78	History-based memory mode prediction for improving memory performance	claim
228	78	Bio-inspired flight control and visual search with CNN technology	claim
229	78	An efficient approach for error diagnosis in HDL design	claim
230	78	Direct mode coding for bi-predictive pictures in the JVT standard	claim
231	77	Inductive interconnect width optimization for low power	claim
232	77	Table look-up based compact modeling for on-chip interconnect timing and noise analysis	claim
233	77	A 1.4G samples/sec comb filter design for decimation of sigma-delta modulator output	claim
234	77	A CMOS analog continuous-time FIR filter for 1Gbps cable equalizer	claim
235	77	General iterative heuristics for VLSI multiobjective partitioning	claim
236	76	A 24-bit floating-point audio DSP controller supporting fast exponentiation	claim
237	76	Loop scheduling for minimizing schedule length and switching activities	claim
238	75	Improved current-source sizing for high-speed high-accuracy current steering D/A converters	claim
239	75	VLSI implementation of a real-time video watermark embedder and detector	claim
240	74	Signaling capacity of FR4 PCB traces for chip-to-chip communication	claim
241	73	Realization of electronically tunable ladder filters using multi-output current controlled conveyors	claim
242	72	Classification of synchronized states in CNNs with higher order cells	claim
243	72	Roundoff noise minimization in two-dimensional state-space digital filters using error feedback	claim
244	72	Design and implementation of high-speed arbiter for large scale VOQ crossbar switches	claim
245	71	Noise constraint driven placement for mixed signal designs	claim
246	71	A low power asynchronous GF(2/sup 173/) ALU for elliptic curve crypto-processor	claim
247	69	A modular sensor microsystem utilizing a universal interface circuit	claim
248	66	A triple port RAM based low power commutator architecture for a pipelined FFT processor	claim
249	66	System observability and nonlinear parameter identification of nonylphenol biodegradation kinetics	claim
250	64	Matching of low-noise amplifiers at high frequencies	claim
251	62	Simple noise formulas for MOS analog design	claim

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