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LCTRTS
2010
Springer

268views System Software» more LCTRTS 2010»

Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications

14 years 5 days ago

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With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to- market projections, Transaction Level Modeling and Platform Aware Design are seen as...

Ines Viskic, Lochi Lo Chi Yu Lo, Daniel Gajski

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Id	Views	Title	Status

1	268	Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications	claim
2	236	Analysis and approximation for bank selection instruction minimization on partitioned memory architecture	claim
3	236	RNFTL: a reuse-aware NAND flash translation layer for flash memory	claim
4	207	Elastic computing: a framework for transparent, portable, and adaptive multi-core heterogeneous computing	claim
5	206	Contracts for modular discrete controller synthesis	claim
6	197	Modeling structured event streams in system level performance analysis	claim
7	190	Cache vulnerability equations for protecting data in embedded processor caches from soft errors	claim
8	182	Compiler directed network-on-chip reliability enhancement for chip multiprocessors	claim
9	179	Translating concurrent action oriented specifications to synchronous guarded actions	claim
10	178	Versatile system-level memory-aware platform description approach for embedded MPSoCs	claim
11	175	Semi-automatic derivation of timing models for WCET analysis	claim
12	173	Operation and data mapping for CGRAs with multi-bank memory	claim
13	154	Improving both the performance benefits and speed of optimization phase sequence searches	claim
14	152	An efficient code update scheme for DSP applications in mobile embedded systems	claim
15	150	Sampling-based program execution monitoring	claim
16	130	Integrating safety analysis into the model-based development toolchain of automotive embedded systems	claim
17	128	Resilience analysis: tightening the CRPD bound for set-associative caches	claim

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