DSD 2009 - PDF Preprint Papers

DSD 2009 Euromicro Symposium on Digital Systems Design

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DSD
2009
IEEE

387views Hardware» more DSD 2009»

Architecture and DSP Implementation of a DVB-S2 Baseband Demodulator

14 years 6 months ago

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—This paper presents the design and implementation of a baseband demodulator for DVB-S2 satellite receivers. In order to meet the requirements of different complex and multidomai...

Panayiotis Savvopoulos, Nikolaos Papandreou, Theod...

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Id	Views	Title	Status

1	387	Architecture and DSP Implementation of a DVB-S2 Baseband Demodulator	claim
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3	152	ARROW - A Generic Hardware Fault Injection Tool for NoCs	claim
4	148	SIMD Architectural Enhancements to Improve the Performance of the 2D Discrete Wavelet Transform	claim
5	147	A High Performance Hardware Architecture for One Bit Transform Based Motion Estimation	claim
6	145	High Performance Image Processing on a Massively Parallel Processor Array	claim
7	144	Composable Resource Sharing Based on Latency-Rate Servers	claim
8	141	A Reconfigurable Frame Interpolation Hardware Architecture for High Definition Video	claim
9	136	An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload	claim
10	133	Deductive Fault Simulation for Asynchronous Sequential Circuits	claim
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12	124	Network-on-Chip Architecture Exploration Framework	claim
13	118	The Case for a Balanced Decomposition Process	claim
14	118	Internet-Router Buffered Crossbars Based on Networks on Chip	claim
15	118	On the Risk of Fault Coupling over the Chip Substrate	claim
16	111	Robustness Check for Multiple Faults Using Formal Techniques	claim
17	106	Model-Driven Design of Embedded Multimedia Applications on SoCs	claim
18	105	Design of a Highly Dependable Beamforming Chip	claim
19	104	Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism	claim
20	95	The Parallel Sieve Method for a Virus Scanning Engine	claim
21	93	Transactions Sequence Tracking by means of Dynamic Binary Instrumentation of TLM Models	claim
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23	92	Synthesizing Reversible Circuits for Irreversible Functions	claim
24	90	Instruction Precomputation for Fault Detection	claim
25	88	A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor	claim
26	85	Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail Test Environment	claim
27	84	Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures	claim
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29	77	Pulse Generation for On-chip Data Transmission	claim
30	71	Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables	claim

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