FPGA 1999 - PDF Preprint Papers

FPGA 1999 International ACM Symposium on Field-Programmable Gate Arrays

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FPGA
1999
ACM

174views FPGA» more FPGA 1999»

Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs

14 years 3 months ago

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Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimized towards specific applications...

Peter Kollig, Bashir M. Al-Hashimi

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Id	Views	Title	Status

1	174	Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs	claim
2	165	Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution	claim
3	163	Memory Interfacing and Instruction Specification for Reconfigurable Processors	claim
4	155	FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density	claim
5	144	Configuration Caching Vs Data Caching for Striped FPGAs	claim
6	142	Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems	claim
7	139	Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs	claim
8	137	A New High Density and Very Low Cost Reprogrammable FPGA Architecture	claim
9	133	A FPGA-Based Hardware Implementation of Generalized Profile Search Using Online Arithmetic	claim
10	132	The Wave Pipeline Effect on LUT-Based FPGA Architectures	claim
11	130	Hybrid Product Term and LUT Based Architectures Using Embedded Memory Blocks	claim
12	124	Don't Care Discovery for FPGA Configuration Compression	claim
13	123	Procedural Texture Mapping on FPGAs	claim
14	122	Exploiting FPGA-Features During the Emulation of a Fast Reactive Embedded System	claim
15	115	Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density	claim
16	104	Universal Switch Blocks for Three-Dimensional FPGA Design	claim

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