FPGA 2005 - PDF Preprint Papers

FPGA 2005 International ACM Symposium on Field-Programmable Gate Arrays

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed FPGA-2005 Paper

click to vote

FPGA
2005
ACM

215views FPGA» more FPGA 2005»

Design, layout and verification of an FPGA using automated tools

14 years 5 months ago

Download www.eecg.toronto.edu

Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately ...

Ian Kuon, Aaron Egier, Jonathan Rose

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	215	Design, layout and verification of an FPGA using automated tools	claim
2	195	Sparse Matrix-Vector multiplication on FPGAs	claim
3	174	64-bit floating-point FPGA matrix multiplication	claim
4	158	Automated synthesis for asynchronous FPGAs	claim
5	156	Design of programmable interconnect for sublithographic programmable logic arrays	claim
6	137	HARP: hard-wired routing pattern FPGAs	claim
7	122	Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability	claim
8	121	Floating-point sparse matrix-vector multiply for FPGAs	claim
9	107	Instruction set extension with shadow registers for configurable processors	claim
10	105	Soft error rate estimation and mitigation for SRAM-based FPGAs	claim
11	97	Techniques for synthesizing binaries to an advanced register/memory structure	claim
12	95	The Stratix II logic and routing architecture	claim
13	90	Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits	claim
14	80	Simultaneous timing-driven placement and duplication	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers