HPCA 2007 - PDF Preprint Papers

HPCA 2007 International Symposium on High-Performance Computer Architecture

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HPCA
2007
IEEE

211views Distributed And Parallel Com...» more HPCA 2007»

An Adaptive Cache Coherence Protocol Optimized for Producer-Consumer Sharing

14 years 5 months ago

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Shared memory multiprocessors play an increasingly important role in enterprise and scientiﬁc computing facilities. Remote misses limit the performance of shared memory applicat...

Liqun Cheng, John B. Carter, Donglai Dai

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Id	Views	Title	Status

1	211	An Adaptive Cache Coherence Protocol Optimized for Producer-Consumer Sharing	claim
2	181	Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling	claim
3	175	Evaluating MapReduce for Multi-core and Multiprocessor Systems	claim
4	173	Application-Level Correctness and its Impact on Fault Tolerance	claim
5	170	Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers	claim
6	170	An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors	claim
7	166	Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications	claim
8	149	LogTM-SE: Decoupling Hardware Transactional Memory from Caches	claim
9	142	A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures	claim
10	140	Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors	claim
11	131	A Burst Scheduling Access Reordering Mechanism	claim
12	126	Colorama: Architectural Support for Data-Centric Synchronization	claim
13	121	Concurrent Direct Network Access for Virtual Machine Monitors	claim
14	121	A Scalable, Non-blocking Approach to Transactional Memory	claim
15	121	Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures	claim
16	118	A Memory-Level Parallelism Aware Fetch Policy for SMT Processors	claim
17	116	Illustrative Design Space Studies with Microarchitectural Regression Models	claim
18	115	Interconnect-Centric Computing	claim
19	115	Optical Interconnect Opportunities for Future Server Memory Systems	claim
20	115	Accelerating and Adapting Precomputation Threads for Effcient Prefetching	claim
21	114	HARD: Hardware-Assisted Lockset-based Race Detection	claim
22	113	Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines	claim
23	105	Improving Branch Prediction and Predicated Execution in Out-of-Order Processors	claim
24	104	Perturbation-based Fault Screening	claim
25	102	Exploiting Postdominance for Speculative Parallelization	claim
26	96	A Domain-Specific On-Chip Network Design for Large Scale Cache Systems	claim
27	96	MemTracker: Efficient and Programmable Support for Memory Access Monitoring and Debugging	claim
28	89	Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping	claim
29	87	Interactions Between Compression and Prefetching in Chip Multiprocessors	claim
30	77	Implications of Device Timing Variability on Full Chip Timing	claim

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