ISLPED 1999 - PDF Preprint Papers

ISLPED 1999 International Symposium on Low Power Electronics and Design

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed ISLPED-1999 Paper

click to vote

ISLPED
1999
ACM

236views Hardware» more ISLPED 1999»

Modeling and automating selection of guarding techniques for datapath elements

14 years 3 months ago

Download www.cecs.uci.edu

While guarded evaluation has proven an effective energy saving technique in arithmetic circuits, good methodologies do not exist for determining when and how to guard for maximal ...

William E. Dougherty, Donald E. Thomas

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	236	Modeling and automating selection of guarding techniques for datapath elements	claim
2	177	Low power synthesis of dual threshold voltage CMOS VLSI circuits	claim
3	160	Mixed-swing quadrail for low power dual-rail domino logic	claim
4	150	Using dynamic cache management techniques to reduce energy in a high-performance processor	claim
5	143	Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation	claim
6	137	Energy-efficient design of battery-powered embedded systems	claim
7	131	Challenges in clockgating for a low power ASIC methodology	claim
8	129	Power scalable processing using distributed arithmetic	claim
9	107	The impact of battery capacity and memory bandwidth on CPU speed-setting: a case study	claim
10	103	A low energy architecture for fast PN acquisition	claim
11	102	Circuit styles and strategies for CMOS VLSI design on SOI	claim
12	100	Selective instruction compression for memory energy reduction in embedded systems	claim
13	100	Ultra-low power digital subthreshold logic circuits	claim
14	98	Passive precharge and rippled power logic (PPRPL)	claim
15	91	Stochastic modeling of a power-managed system: construction and optimization	claim
16	90	Low power RF integrated circuits: principles and practice	claim
17	90	Way-predicting set-associative cache for high performance and low energy consumption	claim
18	89	Clock distribution using multiple voltages	claim
19	86	Power macro-models for DSP blocks with application to high-level synthesis	claim
20	85	Non-stationary effects in trace-driven power analysis	claim
21	84	An architectural solution for the inductive noise problem due to clock-gating	claim
22	72	The design of a low energy FPGA	claim
23	71	System-level power optimization: techniques and tools	claim
24	70	Global register allocation for minimizing energy consumption	claim
25	65	Efficient switching activity computation during high-level synthesis of control-dominated designs	claim
26	63	Energy-efficient dynamic circuit design in the presence of crosstalk noise	claim
27	47	Databus charge recovery: practical considerations	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers