MICRO 1999 - PDF Preprint Papers

MICRO 1999 IEEE/ACM International Symposium on Microarchitecture

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MICRO
1999
IEEE

143views Hardware» more MICRO 1999»

Code Transformations to Improve Memory Parallelism

14 years 5 months ago

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Current microprocessors incorporate techniques to exploit instruction-level parallelism (ILP). However, previous work has shown that these ILP techniques are less effective in rem...

Vijay S. Pai, Sarita V. Adve

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Id	Views	Title	Status

1	143	Code Transformations to Improve Memory Parallelism	claim
2	138	Automatic and Efficient Evaluation of Memory Hierarchies for Embedded Systems	claim
3	138	New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies	claim
4	138	Dynamic 3D Graphics Workload Characterization and the Architectural Implications	claim
5	136	Read-After-Read Memory Dependence Prediction	claim
6	131	Value Prediction for Speculative Multithreaded Architectures	claim
7	123	Improving Branch Predictors by Correlating on Data Values	claim
8	115	Fetch Directed Instruction Prefetching	claim
9	110	Balance Scheduling: Weighting Branch Tradeoffs in Superblocks	claim
10	109	Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results	claim
11	108	Exploiting ILP in Page-based Intelligent Memory	claim
12	105	DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design	claim
13	104	Control Independence in Trace Processors	claim
14	102	Evaluation of a High Performance Code Compression Method	claim
15	100	A Superscalar 3D Graphics Engine	claim
16	98	Access Region Locality for High-Bandwidth Processor Memory System Design	claim
17	98	Instruction Fetch Mechanisms for Multipath Execution Processors	claim
18	91	The Use of Multithreading for Exception Handling	claim
19	84	Low-Cost Branch Folding for Embedded Applications with Small Tight Loops	claim
20	71	Selective Cache Ways: On-Demand Cache Resource Allocation	claim

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