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Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems

13 years 7 months ago

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In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...

HeungJun Jeon, Yong-Bin Kim, Minsu Choi

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