VTS 2007 - PDF Preprint Papers

VTS 2007 IEEE VLSI Test Symposium

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VTS
2007
IEEE

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Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code

14 years 5 months ago

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Conventional error correcting code (ECC) schemes used in memories and caches cannot correct double bit errors caused by a single event upset (SEU). As memory density increases, mu...

Avijit Dutta, Nur A. Touba

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Id	Views	Title	Status

1	203	Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code	claim
2	143	RTL Test Point Insertion to Reduce Delay Test Volume	claim
3	135	High Level Synthesis of Degradable ASICs Using Virtual Binding	claim
4	129	Supply Voltage Noise Aware ATPG for Transition Delay Faults	claim
5	116	Case Study: Soft Error Rate Analysis in Storage Systems	claim
6	114	Parameter Estimation for a Model with Both Imperfect Test and Repair	claim
7	105	Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack Resistance	claim
8	103	At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester	claim
9	102	Transformer-Coupled Loopback Test for Differential Mixed-Signal Specifications	claim
10	100	Using Scan-Dump Values to Improve Functional-Diagnosis Methodology	claim
11	95	Delay Test Quality Evaluation Using Bounded Gate Delays	claim
12	89	Test Set Reordering Using the Gate Exhaustive Test Metric	claim
13	85	Minimizing the Impact of Scan Compression	claim
14	79	Using Multiple Expansion Ratios and Dependency Analysis to Improve Test Compression	claim
15	71	Optimizing Test Length for Soft Faults in DRAM Devices	claim

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