Another Look at the Sequential Multiplier over Normal Bases

—The Massey-Omura multiplier is a well-known sequential multiplier over finite fields GF(2m ), which can perform multiplication in m clock cycles for the normal basis. In this article, we propose a new architecture to carry out the sequential multiplier using normal basis. The time complexity in each cycle of this new multiplier is O(1) and the number of inputs is lower down to m+1, instead of 2m, which is the number needed for most previous multipliers. These merits make it easier to the VLSI implementation.1 Keywords—finite fields, sequential multiplier, normal basis, VLSI implementation

• Type: Conference
• Year: 2006
• Where: APCCAS
• Authors: Zih-Heng Chen, Ming-Haw Jing, Trieu-Kien Truong, Yaotsu Chang
• Keywords: APCCAS 2006, Hardware, Normal Basis, Sequential Multiplier, Well-known Sequential Multiplier