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ASAP
2006
IEEE

A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing

14 years 5 months ago
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing
Massively parallel processor array architectures can be used as hardware accelerators for a plenty of dataflow dominant applications. Bilateral filtering is an example of a state-of-the-art algorithm in medical imaging, which falls in the class of 2D adaptive filter algorithms. In this paper, we propose a semi-automatic mapping methodology for the generation of hardware accelerators for such a generic class of adaptive filtering applications in image processing. The final architecture deliver similar synthesis results as a hand-tuned design.
Hritam Dutta, Frank Hannig, Jürgen Teich, Ben
Added 10 Jun 2010
Updated 10 Jun 2010
Type Conference
Year 2006
Where ASAP
Authors Hritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, Heinz Hornegger
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