Towards the System-on-Chip Realization of a Sensorless Vector Controller with Microsecond-order Computation Time

— The aim of this research is to implement sensorless vector control algorithms on a single, eventually reconfigurable, chip, with a computation timing constraint of, at most, 1-6 microseconds, and a concern for implementation cost. In this article, we discuss the implementation problems and tradeoffs involved in meeting these goals on Field-Programmable Gate Arrays (FPGAs). To be able to fit a complete induction motor vector controller on a single, inexpensive FPGA chip, we estimate the area/time requirements of each module involved in sensorless vector control. We discuss, in particular, the tradeoffs of implementing the key modules, the speed and flux observers and the Clarke and Park transformations. The speed and flux observers here under consideration are extended Kalman filter-based.

• Type: Conference
• Year: 2006
• Where: CCECE
• Authors: Rachid Beguenane, Jean-Gabriel Mailloux, Stéphane Simard, Arnaud Tisserand
• Keywords: CCECE 2006, Computation Timing Constraint, Electrical And Computer Engineering, Sensorless Vector Control, Vector Control Algorithms