On-Chip Test Generation Using Linear Subspaces

A central problem in built-in self test (BIST) is how to efficiently generate a small set of test vectors that detect all targeted faults. We propose a novel solution that uses linear algebraic concepts to partition the vector space of tests into subspaces (clusters). A subspace is defined by a compact set of basis vectors. We give an algorithm to compute sets of basis vectors defining the clusters. We also describe a low-cost logic circuit based on Gray codes that reproduces the subspaces from these basis vectors. Experimental results are presented which show that this approach reduces on-chip hardware overhead and test application time, while also guaranteeing full fault coverage.

• Type: Conference
• Year: 2006
• Where: ETS
• Authors: Ramashis Das, Igor L. Markov, John P. Hayes
• Keywords: Basis Vectors, Built-in Self Test, ETS 2006, Hardware, Test Vectors