Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism

This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. strate that these interconnects abstract the interconnect details and provide predictability in the data transfer, which are desirable not only for the functional domain but also for the test application. The proposed wrapper is implemented in VHDL and integrated to the Æthereal NoC. The results show the impact of of bandwidth in the core test time. The wrapper area and core test time are compared with a wrapper design for dedicated TAM. 1

• Type: Conference
• Year: 2006
• Where: ETS
• Authors: Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes
• Keywords: Core Test Time, ETS 2006, Hardware, Interconnect, Wrapper Design