— We present a field programmable gate array (FPGA) implementation of a turbo-like decoder for a serially concatenated pulse-position modulation (SCPPM) code. NASA developed this coded modulation scheme for deep space communications from Mars. Under a nominal mission condition, the SCPPM coded system can operate within a one dB signal energy gap from capacity. The structure of SCPPM makes direct application of the conventional turbo decoding algorithm very inefficient. Here, we describe techniques to increase the throughput and performance of a hardware SCPPM decoder. Using our optimizations, we demonstrate a 6 mega-bits per second (Mbps) decoder realization on a single FPGA. Extension to a higher data rate decoder using multiple FPGAs is readily achievable. Similar codes designed for the optical channel can benefit from our optimization techniques.
Michael K. Cheng, Bruce E. Moision, Jon Hamkins, M