Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs

This paper presents a minimum area, low-power driven clustering algorithm for coarse-grained, antifuse-based FPGAs under delay constraints. The algorithm accurately predicts logic replication caused by timing constraint during the low-power driven clustering. This technique reduces size of duplicated logic substantially, resulting in benefits in area, delay, and power dissipation. First, we build power-delay curves at nodes with the aid of the prediction algorithm. Next, we choose the best cluster starting from primary outputs moving backward in the circuit based on these curves. Experimental results show 16% and 20% reduction in dynamic and leakage power dissipation with 18% area reduction compared to the results of clustering without the replication prediction. Categories and Subject Descriptors J.6 [Computer-aided engineering]: Computer-aided design (CAD) General Terms Algorithm Keywords FPGA, Antifuse, Clustering, Power

• Type: Conference
• Year: 2006
• Where: GLVLSI
• Authors: Chang Woo Kang, Massoud Pedram
• Keywords: Clustering Algorithm, GLVLSI 2006, Low-power Driven Clustering, Power Dissipation, VLSI