Parallel FPGA-based all-pairs shortest-paths in a directed graph

With rapid advances in VLSI technology, Field Programmable Gate Arrays (FPGAs) are receiving the attention of the Parallel and High Performance Computing community. In this paper, we propose a highly parallel FPGA design for the Floyd-Warshall algorithm to solve the allpairs shortest-paths problem in a directed graph. Our work is motivated by a computationally intensive bio-informatics application that employs this algorithm. The design we propose makes efficient and maximal utilization of the large amount of resources available on an FPGA to maximize parallelism in the presence of significant data dependences. Experimental results from a working FPGA implementation on the Cray XD1 show a speedup of 22 over execution on the XD1’s processor.

• Type: Conference
• Year: 2006
• Where: IPPS
• Authors: Uday Bondhugula, Ananth Devulapalli, Joseph Fernando, Pete Wyckoff, P. Sadayappan
• Keywords: Distributed And Parallel Computing, FPGA, IPPS 2006, Parallel Fpga Design, Programmable Gate Arrays