Performance evaluation of wormhole routed network processor-memory interconnects

Network line cards are experiencing ever increasing line rates, random data bursts, and limited space. Hence, they are more vulnerable than other processormemory environments, to create data transfer bottlenecks and hot-spots. Solutions to the memory bandwidth bottleneck are limited by the area available on the line card and network processor I/O pins. As a result, we propose to explore more suitable off-chip interconnect and communication mechanisms that will replace the existing systems and that will provide extraordinary high throughput. We utilize our customdesigned, event-driven, interconnect simulator to evaluate the performance of wormhole routed packet-based off-chip k-ary n-cube interconnect architectures for line cards. Our performance results show that wormhole routed k-ary n-cube based interconnect topologies significantly outperform the existing line card interconnects and they are able to sustain higher traffic loads.

• Type: Conference
• Year: 2006
• Where: IPPS
• Authors: Taskin Koçak, Jacob Engel
• Keywords: Distributed And Parallel Computing, Interconnects, IPPS 2006, Line Card, Network Line Cards