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30

ISMVL
2006
IEEE

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Design Methods for Multiple-Valued Input Address Generators

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Design Methods for Multiple-Valued Input Address Generators

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A multiple-valued input address generator produces a unique address given a multiple-valued input data vector. This paper presents methods to realize multiple-valued input address generators by multi-level networks of p-input q-output memories. It shows a method to simplify the address generators using an auxiliary memory.

Tsutomu Sasao

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Artificial Intelligence | Input Address Generators | ISMVL 2006 | Multiple-valued Input Address | Multiple-valued Input Data |

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Added	12 Jun 2010
Updated	12 Jun 2010
Type	Conference
Year	2006
Where	ISMVL
Authors	Tsutomu Sasao

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