Design Methods for Multiple-Valued Input Address Generators

A multiple-valued input address generator produces a unique address given a multiple-valued input data vector. This paper presents methods to realize multiple-valued input address generators by multi-level networks of p-input q-output memories. It shows a method to simplify the address generators using an auxiliary memory.

• Type: Conference
• Year: 2006
• Where: ISMVL
• Authors: Tsutomu Sasao
• Keywords: Artificial Intelligence, Input Address Generators, ISMVL 2006, Multiple-valued Input Address, Multiple-valued Input Data