Comparing simulation techniques for microarchitecture-aware floorplanning

— Due to the long simulation times of the reference input sets, microarchitects resort to alternative techniques to speed up cycle-accurate simulations. However, the reduction in the runtimes comes with an associated loss of accuracy in replicating the characteristics of the reference sets. In addition, the effect of these inaccuracies on the overall performance can vary across different microarchitecture optimizations or enhancements. In this work, we study and compare two such techniques, reduced input sets and statistical sampling, in the context of microarchitecture-aware floorplanning, a physical design stage, where the objective is to find an IPC-optimal global placement of the blocks of a microprocessor. The variation in the IPC results due the insertion of additional flip-flops on some across-chip wires of the processor that have multicycle delays in nanometer technology nodes. The objective of IPCaware floorplanning is to minimize the amount of pipelining required by th...

• Type: Conference
• Year: 2006
• Where: ISPASS
• Authors: Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar
• Keywords: Input Sets, ISPASS 2006, Long Simulation Times, Reference Sets, Software Engineering