Instruction Scheduling with Release Times and Deadlines on ILP Processors

ILP (Instruction Level Parallelism) processors are being increasingly used in embedded systems. In embedded systems, instructions may be subject to timing constraints. An optimising compiler for ILP processors needs to find a feasible schedule for a set of time-constrained instructions. In this paper, we present a fast algorithm for scheduling instructions with precedence-latency constraints, individual integer release times and deadlines on an ILP processor with multiple functional units. The time complexity of our algorithm is O(n2 log d) + min{O(de), O(ne)} + min{O(ne), O(n2.376 )}, where n is the number of instructions, e is the number of edges in the precedence graph and d is the maximum latency. Our algorithm is guaranteed to find a feasible schedule whenever one exists in the following special cases: 1) one functional unit, arbitrary precedence constraints, latencies in {0, 1}, integer release times and deadlines; 2) two identical functional units, arbitrary precedence constr...

• Type: Conference
• Year: 2006
• Where: RTCSA
• Authors: Hui Wu, Joxan Jaffar, Jingling Xue
• Keywords: Functional Units, Integer Release Times, Multiple Functional Units, Real-Time Computing, RTCSA 2006