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SIPS
2006
IEEE

Carry Prediction and Selection for Truncated Multiplication

14 years 5 months ago
Carry Prediction and Selection for Truncated Multiplication
This paper presents an error compensation method for truncated multiplication. From two n-bit operands, the operator produces an n-bit product with small error compared to the 2n-bit exact product. The method is based on a logical computation followed by a simplification process. The filtering parameter used in the simplification process helps to control the trade-off between hardware cost and accuracy. The proposed truncated multiplication scheme has been synthesized on an FPGA platform. It gives a better accuracy over area ratio than previous well-known schemes such as the constant correcting and variable correcting truncation schemes (CCT and VCT).
Romain Michard, Arnaud Tisserand, Nicolas Veyrat-C
Added 12 Jun 2010
Updated 12 Jun 2010
Type Conference
Year 2006
Where SIPS
Authors Romain Michard, Arnaud Tisserand, Nicolas Veyrat-Charvillon
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