Automated Architectural Exploration for Signal Processing Algorithms

Abstract— This paper presents a design environment for efficiently generating application-specific Intellectual Property (IP) cores for system level signal processing algorithms. We present our view of a framework that combines common electronic design automation (EDA) tools to alleviate the designer from manually constructing the hardware models and analyzing their performance. We use our framework to efficiently implement design optimizations that improve the performance of the overall hardware architectures. Our framework is well suited for designers with a range of signal processing and hardware expertise. Our framework generates the dedicated IP cores and estimates the performance such as area, critical path delay, and latency within seconds. Parts of our framework also compare different hardware designs for various digital signal processing (DSP) algorithms and allows the designer to make architectural decisions earlier in the hardware design process. We use a GUI-based fram...

• Type: Conference
• Year: 2006
• Where: SIPS
• Authors: Ramsey Hourani, Ravi Jenkal, W. Rhett Davis, Winser Alexander
• Keywords: Hardware, Hardware Designs, Signal Processing, SIPS 2006