Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

17

Voted

DFT
2005
IEEE

favoriteEmaildiscussreport

92views VLSI» more DFT 2005»

On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits

14 years 1 months ago

On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits

Download comp.uark.edu

Jia Di, Parag K. Lala, D. P. Vasudevan

Real-time Traffic

DFT 2005 | Hardware |

claim paper

Related Content

» Asynchronous circuits transient faults sensitivity evaluation

» OnChip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanosca...

» Ensemble Dependent Matrix Methodology for ProbabilisticBased Faulttolerant Nanoscale Circu...

» Bilateral Testing of Nanoscale Faulttolerant Circuits

» ATPGbased grading of strong faultsecureness

Post Info
More Details (n/a)

Added	24 Jun 2010
Updated	24 Jun 2010
Type	Conference
Year	2005
Where	DFT
Authors	Jia Di, Parag K. Lala, D. P. Vasudevan

Comments (0)