Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files

Register files are in the critical path of most high-performance processors and their latency is one of the most important factors that limit their size. Our goal is to develop error correction mechanisms at the architecture level. Utilizing this increased robustness, the clock frequencies of the circuits are pushed beyond the point of allowing full voltage swing. This increases the errors observed due to noise and other external factors. The resulting errors are then corrected through the error correction mechanisms. We first develop a realistic model for error probability in register files for a given clock frequency. Then, we present the overall architecture, which allows the error detection computation to be overlapped with other computation in the pipeline. We develop novel techniques that utilize the fact that at a given instance many physical registers are not used in superscalar processors. These underutilized registers are used to store the values of active registers. Our sim...

• Type: Conference
• Year: 2005
• Where: DSN
• Authors: Gokhan Memik, Masud H. Chowdhury, Arindam Mallik, Yehea I. Ismail
• Keywords: Computer Networks, DSN 2005, Error Correction Mechanisms, Error Detection Computation, Register File