Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing

The ever-increasing number of transistors on a chip has resulted in very large scale integration (VLSI) systems whose performance and manufacturing costs are driven by on-chip wiring needs. This paper proposes a low overhead wave-pipelined two-slot time division multiplexed (WP/2-TDM) routing technique that harnesses the inherent intra-clock period wire idleness to implement wire sharing in combination with wave-pipelined circuit techniques. It is illustrated in this paper that WP/2-TDM routing can be readily incorporated into future gigascale integration (GSI) systems to reduce the number of interconnect routing channels in an attempt to contain escalating manufacturing costs. Two case studies, one at the circuit level and one at the system level, are presented to illustrate the advantages of WP/2-TDM routing. The circuit level implementation exhibits more than 40% reduction in wire area, a 30% reduction in silicon area with no increase in dynamic power and no loss of throughput perf...

• Type: Conference
• Year: 2005
• Where: GLVLSI
• Authors: Ajay Joshi, Jeffrey A. Davis
• Keywords: Circuit Level, GLVLSI 2005, Manufacturing Costs, VLSI, WP/2-TDM Routing