FPGA Architecture for Real-Time Video Noise Estimation

This paper proposes a hardware architecture of a video noise estimation algorithm capable of real-time processing. The objectives consist of adapting a computationally demanding noise estimation algorithm to a synthesizable VHDL implementation and achieving realtime performance. This Structure-oriented noise estimation method considers image structure to find intensity-homogeneous blocks. Subsequently, these blocks are included in the averaging process to estimate the noise variance. Generating worst-case estimation error of 3 dB, this spatial noise reduction method is reliable for highly noisy and textured images. The proposed architecture provides a satisfactory compromise between area and processing speed. Furthermore, parameterization of the architecture allows additional flexibility with the scaling of mask sizes that can operate on 3x3 or 5x5 blocks of pixels. The proposed design is targeted to an FPGA device and estimates the noise variance over an interlaced PAL video sequence...

• Type: Conference
• Year: 2006
• Where: ICIP
• Authors: Francois-Xavier Lapalme, Aishy Amer, Chunyan Wang
• Keywords: ICIP 2006, Image Processing, Noise Estimation Algorithm, Noise Estimation Method, Noise Reduction Method, Noise Variance, Video Noise Estimation