Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport

As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural design focus from operation computation to operand transport. Operand bypass networks of out-oforder superscalar processors are particularly demanding of wiring resources. Forwarding path delay has become a limiting factor of processor performance. This paper proposes a novel technology-based methodology to evaluate bypass network configurations by predicting operand transport cost. It combines technology modeling techniques with cycle-accurate simulation of benchmark applications to characterize operand movement and storage requirements. Our analysis shows that the operand transport cost heavily depends on the physical location of functional units (FUs) and instruction steering strategy. We propose a traffic-based placement which places FUs based on the transport distribution pattern; and a geometry-driven inst...

• Type: Conference
• Year: 2005
• Where: IPPS
• Authors: Hongkyu Kim, D. Scott Wills, Linda M. Wills
• Keywords: Distributed And Parallel Computing, IPPS 2005, Operand, Operand Transport, Operand Transport Cost