—This paper presents a method to optimize the power consumption of a pipelined ADC with kT/C noise constraint. The total power dependence on capacitor scaling and stage resolution is investigated. With eight different capacitor scaling functions, near-optimal solution can be obtained. For 12bit pipeline ADC, the power decreases with effective number of bits per stage. This method can be easily extended to other resolution pipeline ADCs.
Yu Lin, Vipul Katyal, Mark Schlarmann, Randall L.