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ISCAS
2005
IEEE

kT/C constrained optimization of power in pipeline ADCs

14 years 5 months ago
kT/C constrained optimization of power in pipeline ADCs
—This paper presents a method to optimize the power consumption of a pipelined ADC with kT/C noise constraint. The total power dependence on capacitor scaling and stage resolution is investigated. With eight different capacitor scaling functions, near-optimal solution can be obtained. For 12bit pipeline ADC, the power decreases with effective number of bits per stage. This method can be easily extended to other resolution pipeline ADCs.
Yu Lin, Vipul Katyal, Mark Schlarmann, Randall L.
Added 25 Jun 2010
Updated 25 Jun 2010
Type Conference
Year 2005
Where ISCAS
Authors Yu Lin, Vipul Katyal, Mark Schlarmann, Randall L. Geiger
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