Digital VLSI OFDM transceiver architecture for wireless SoC design

—This paper presents the VLSI architecture of an OFDM baseband transceiver for wireless communications. The open-/closed-loop carrier recovery achieves the stepping frequency acquisition for high-band RF systems, and the proposed timing recovery cooperated with the self-correcting interpolation realizes an OFDM baseband digital IP design. Hardware sharing and power-of-2 coefficients fulfill this compact transceiver system chip. Simulations show that the receiver can deliver 10% packet error rate (PER) requirement under all specified SNRs for IEEE 802.11a. Using the typical 0.25µm CMOS technology, the chip occupies 3.5×3.5 mm2 area and consumes 109 mW under 2.5 V power supply.

• Type: Conference
• Year: 2005
• Where: ISCAS
• Authors: Wei-Hsiang Tseng, Ching-Chi Chang, Chorng-Kuang Wang
• Keywords: Baseband Digital Ip, ISCAS 2005, OFDM Baseband, OFDM Baseband Transceiver