An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arrays

—This paper presents a memory-conscious mapping methodology of computational intensive applications on coarse-grain reconfigurable arrays. By exploiting the inherent abundant amounts of data reuse in DSP applications, the methodology tries to minimize the data memory bandwidth, which constitutes a major bottleneck for the applications performance. This is achieved by using the distributed foreground storage elements in the architecture and by the proper placing operations in the processing elements. The methodology considers a realistic 2-Dimensional coarse-grain reconfigurable architecture template which can model a large number of existing coarse-grain architectures. The experimental results show that memory accesses and execution time are reduced since the mapping methodology efficiently exploits the data reuse opportunities. The need for taking into account memory bandwidth limitations is also illustrated.

• Type: Conference
• Year: 2005
• Where: ISCAS
• Authors: Michalis D. Galanis, Gregory Dimitroulakos, Constantinos E. Goutis
• Keywords: Coarse-grain Reconfigurable Arrays, ISCAS 2005, Mapping Methodology, Methodology