Optimization Techniques for ADL-Driven RTL Processor Synthesis

Nowadays, Architecture Description Languages (ADLs) are getting popular to speed up the development of complex SoC design, by performing the design space explon a higher level of abstraction. This increase in raction level traditionally comes at the cost of low performance of the final Application Specific Instructionset Processor (ASIP) implementation, which is generated automatically from the ADL. There is a pressing need of novel optimization techniques for high level synthesis from ADLs, to compensate for this loss of performance. Two important aspects of these optimizations are the efficient usage of available structural information in the high level architecture descriptions and prudent pruning of overhead, introduced by mapping from ADL to Register Transfer Level (RTL). In this paper, we present two high level optimization techniques, path sharing and decision minimization. These optimization techniques are shown to be of lower complexity, by at least two orders, compared to...

• Type: Conference
• Year: 2005
• Where: RSP
• Authors: Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
• Keywords: Architecture Description Languages, Architecture Descriptions, Optimization Techniques, Rapid System Prototyping, RSP 2005