Coupling aware timing optimization and antenna avoidance in layer assignment

The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which consider only wire self capacitance become inadequate since the wire delay is affected more by coupling capacitance in ultra-deep submicron designs. Furthermore, the technology scaling dramatically increases the likelihood of the antenna problem in manufacturing and requests corresponding considerations in the routing stage. In this paper, we propose techniques that can be applied to handle the coupling aware timing and the antenna problem simultaneously during layer assignment which is an important step between global routing and detailed routing. An improved probabilistic coupling capacitance model is suggested for coupling aware timing optimization without performing track assignment. The antenna avoidance problem is modeled as a tree partitioning problem with a linear time optimal algorithm solution. This al...

• Type: Conference
• Year: 2005
• Where: ISPD
• Authors: Di Wu, Jiang Hu, Rabi N. Mahapatra
• Keywords: Antenna Problem, Coupling Aware Timing, Coupling Capacitance, Hardware, ISPD 2005