Self-correction of FPGA-Based Control Units

This paper presents a self-correcting control unit design using Hamming codes for finite state machine (FSM) state encoding. The adopted technique can correct single-bit errors and detect two-bit errors in the FSM register within the same clock cycle. The main contribution is the development of a parameterizable VHDL package and the respective error-correcting modules, which can easily be added to an FSM specification using any state assignment strategy and having any number of inputs, outputs and states. Besides of application to FSM error correction, the developed tools can easily be adapted to other applications where error detection and correction is required.

• Type: Conference
• Year: 2005
• Where: ICESS
• Authors: Iouliia Skliarova
• Keywords: FSM Register, FSM Specification, ICESS 2005, Self-correcting Control Unit