This paper presents a design methodology for RF CMOS Low Noise Amplifiers (LNA). This methodology uses a current–based MOSFET model, which allows a detailed analysis of an LNA for all MOSFET’s inversion regions. Design equations, including the induced gate noise in MOS devices are also presented and a design example with simulation results is shown. Categories and Subject Descriptors B.7.1 [ASIC]: Circuit design and simulation, RF integrated circuits, low noise amplifiers. General Terms Theory, design. Keywords CMOS, RF, LNA, noise.