A Global Timed Bisimulation Preserving Abstraction for Parametric Time-Interval Automata

Timed Bisimulation Preserving Abstraction for Parametric Time-Interval Automata Akio Nakata, Tadaaki Tanimoto, Suguru Sasaki, Teruo Higashino Department of Information Networking, Graduate School of Information Science and Technology, Osaka University, Suita, Osaka 565-0871, Japan In the development of real-time (communicating) hardware or embedded-software systems, it is frequently the case that we want to refine/optimize the system’s internal behavior while preserving the external timed I/O behavior (that is, the interface protocol). In such a design refinement, modification of the systems’ internal branching structures, as well as re-scheduling of internal actions, may frequently occur. Our goal is, then, to ensure that such branch optimization and re-scheduling of internal actions preserve the systems’ external timed behavior, which is typically formalized by the notion of (timed) testing equivalence since it is less sensitive to the difference of internal branching stru...

• Type: Conference
• Year: 2004
• Where: ATVA
• Authors: Tadaaki Tanimoto, Suguru Sasaki, Akio Nakata, Teruo Higashino
• Keywords: ATVA 2004, External Timed I/o, Internal Actions, Internal Branching Structures