Multiple Restricted Multiplication

Abstract. This paper focuses on a class of problem relating to the multiplication of a single number by several coefficients that, while not constant, are drawn from a finite set of constants that change with time. To minimize the number of operations, we present the formulation as a form of common sub-expression elimination. The proposed scheme avoids the implementation of full multiplication. In addition, an efficient implemenation is presented targeting the Xilinx Virtex / Virtex-II family of FPGAs. We also introduce a novel use of Integer Linear Programming for finding solutions to the minimum-cost of such a multiplication problem. Our formulation results in area savings even for modest problem sizes.

• Type: Conference
• Year: 2004
• Where: FPL
• Authors: Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung
• Keywords: Common Sub-expression Elimination, FPL 2004, Modest Problem Sizes, Multiplication Problem