Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures

The growing dominance of wire delays at future technology points renders a microprocessor communication-bound. Clustered microarchitectures allow most dependence chains to execute without being affected by long on-chip wire latencies. They also allow faster clock speeds and reduce design complexity, thereby emerging as a popular design choice for future microprocessors. However, a centralized data cache threatens to be the primary bottleneck in highly clustered systems. The paper attempts to identify the most complexity-effective approach to alleviate this bottleneck. While decentralized cache organizations have been proposed, they introduce excessive logic and wiring complexity. The paper evaluates if the performance gains of a decentralized cache are worth the increase in complexity. We also introduce and evaluate the behavior of Cluster Prefetch - the forwarding of data values to a cluster through accurate address prediction. Our results show that the success of this technique depe...

• Type: Conference
• Year: 2004
• Where: ICS
• Authors: Rajeev Balasubramonian
• Keywords: Centralized Data Cache, Decentralized Cache, Decentralized Cache Organizations, ICS 2004, Theoretical Computer Science