High-Level Energy Estimation for ARM-Based SOCs

In recent years, power consumption has become a critical concern for many VLSI systems. Whereas several case studies demonstrate that technology-, layout-, and gate-level techniques offer power savings of a factor of two or less, architecture and system-level optimization can often result in orders of magnitude lower power consumption. Therefore, the energy-efficient design of portable, battery-powered systems demands an early assessment, i.e., at the algorithmic and architectural levels, of the power consumption of the applications they target. Addressing this issue, we developed an energy-aware architectural design exploration and analysis tool for ARM based system-on-chip designs. The tool integrates the behavior and energy models of several user-defined, custom processing units as an extension to the cycle-accurate instruction-level simulator for the ARM low-power processor family, called the ARMulator. The models we implemented take into account the particular class, e.g., datap...

• Type: Conference
• Year: 2004
• Where: SAMOS
• Authors: Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, Petri Liuha
• Keywords: Architectural Level, Lower Power Consumption, Power Consumption, SAMOS 2004