Congestion reduction in traditional and new routing architectures

In dense integrated circuit designs, management of routing congestion is essential; an over congested design may be unroutable. Many factors influence congestion: placement, routing, and routing architecture all contribute. Previous work has shown that different placement tools can have substantially different demands for each routing layer; our objective is to develop methods that allow “tuning” of interconnect topologies to match routing resources. We focus on congestion minimization for both Manhattan and non-Manhattan routing architectures, and have two main contributions. First, we combine prior heuristics for non-Manhattan Steiner trees and Preferred Direction Steiner trees into a hybrid approach that can handle arbitrary routing directions, via minimization, and layer assignment of edges simultaneously. Second, we present an effective method to adjust Steiner tree topologies to match routing demand to resource, resulting in lower congestion and better routability. Categori...

• Type: Conference
• Year: 2003
• Where: GLVLSI
• Authors: Ameya R. Agnihotri, Patrick H. Madden
• Keywords: GLVLSI 2003, Non-Manhattan Routing Architectures, Routing, Steiner Trees, VLSI