Zero overhead watermarking technique for FPGA designs

FPGAs, because of their re-programmability, are becoming very popular for creating and exchanging VLSI intellectual properties (IPs) in the reuse-based design paradigm. Existing watermarking and fingerprinting techniques successfully embed identification information into FPGA designs to deter IP infringement. However, such methods incur timing and/or resource overhead, unpredictable at times, which causes performance degradation. In this paper, we propose a new FPGA watermarking technique that guarantees zero design overhead. Our approach consists of two phases. First we design as usual to obtain the best, possible, quality IP. Then we map the required signature to additional timing constraints on carefully selected nets and redo a small portion of the design (e.g. place and route). The FPGA configuration bitstream for the resulting watermarked design will be significantly different from the original design, which provides us with a strong proof of authorship. The watermarking techniq...

• Type: Conference
• Year: 2003
• Where: GLVLSI
• Authors: Adarsh K. Jain, Lin Yuan, Pushkin R. Pari, Gang Qu
• Keywords: Design, Design Overhead, FPGA, GLVLSI 2003, VLSI